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shader_recompiler: Implement V_ADD_F64 and loading 64-bit float from SGPR. (#3483)

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This commit is contained in:
squidbus
2025-08-29 18:11:21 -07:00
committed by GitHub
parent bfa5c508ce
commit 32244c097c
3 changed files with 10 additions and 1 deletions
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2
src/shader_recompiler/frontend/translate/translate.cpp
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@@ -367,7 +367,7 @@ T Translator::GetSrc64(const InstOperand& operand) {
const auto value_lo = ir.GetScalarReg(IR::ScalarReg(operand.code));
const auto value_hi = ir.GetScalarReg(IR::ScalarReg(operand.code + 1));
if constexpr (is_float) {
UNREACHABLE();
value = ir.PackDouble2x32(ir.CompositeConstruct(value_lo, value_hi));
} else {
value = ir.PackUint2x32(ir.CompositeConstruct(value_lo, value_hi));
}

1
src/shader_recompiler/frontend/translate/translate.h
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@@ -149,6 +149,7 @@ public:
void V_READLANE_B32(const GcnInst& inst);
void V_WRITELANE_B32(const GcnInst& inst);
void V_ADD_F32(const GcnInst& inst);
void V_ADD_F64(const GcnInst& inst);
void V_SUB_F32(const GcnInst& inst);
void V_SUBREV_F32(const GcnInst& inst);
void V_MUL_F32(const GcnInst& inst);

8
src/shader_recompiler/frontend/translate/vector_alu.cpp
View File

@@ -392,6 +392,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
return V_CVT_PK_U8_F32(inst);
case Opcode::V_LSHL_B64:
return V_LSHL_B64(inst);
case Opcode::V_ADD_F64:
return V_ADD_F64(inst);
case Opcode::V_ALIGNBIT_B32:
return V_ALIGNBIT_B32(inst);
case Opcode::V_ALIGNBYTE_B32:
@@ -435,6 +437,12 @@ void Translator::V_ADD_F32(const GcnInst& inst) {
SetDst(inst.dst[0], ir.FPAdd(src0, src1));
}
void Translator::V_ADD_F64(const GcnInst& inst) {
const IR::F64 src0{GetSrc64<IR::F64>(inst.src[0])};
const IR::F64 src1{GetSrc64<IR::F64>(inst.src[1])};
SetDst64(inst.dst[0], ir.FPAdd(src0, src1));
}
void Translator::V_SUB_F32(const GcnInst& inst) {
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
const IR::F32 src1{GetSrc<IR::F32>(inst.src[1])};