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shader_recompiler: Fix ImageRead/Write and StoreBufferFormatF32 types.

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This commit is contained in:
squidbus 2024-12-25 15:59:27 -08:00
parent 11eb7413fb
commit 4702b53b92
4 changed files with 10 additions and 10 deletions
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6
src/shader_recompiler/backend/spirv/emit_spirv_image.cpp
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@ -238,7 +238,7 @@ Id EmitImageRead(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id lod
} }
texel = ctx.OpImageRead(color_type, image, coords, operands.mask, operands.operands); texel = ctx.OpImageRead(color_type, image, coords, operands.mask, operands.operands);
} }
return !texture.is_integer ? ctx.OpBitcast(ctx.U32[4], texel) : texel; return texture.is_integer ? ctx.OpBitcast(ctx.F32[4], texel) : texel;
} }
void EmitImageWrite(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id lod, Id ms, void EmitImageWrite(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id lod, Id ms,
@ -253,8 +253,8 @@ void EmitImageWrite(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id
} else if (Sirit::ValidId(lod)) { } else if (Sirit::ValidId(lod)) {
LOG_WARNING(Render, "Image write with LOD not supported by driver"); LOG_WARNING(Render, "Image write with LOD not supported by driver");
} }
ctx.OpImageWrite(image, coords, ctx.OpBitcast(color_type, color), operands.mask, const Id texel = texture.is_integer ? ctx.OpBitcast(color_type, color) : color;
operands.operands); ctx.OpImageWrite(image, coords, texel, operands.mask, operands.operands);
} }
} // namespace Shader::Backend::SPIRV } // namespace Shader::Backend::SPIRV

4
src/shader_recompiler/frontend/translate/vector_memory.cpp
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@ -328,7 +328,7 @@ void Translator::BUFFER_STORE_FORMAT(u32 num_dwords, const GcnInst& inst) {
const IR::VectorReg src_reg{inst.src[1].code}; const IR::VectorReg src_reg{inst.src[1].code};
std::array<IR::Value, 4> comps{}; std::array<IR::F32, 4> comps{};
for (u32 i = 0; i < num_dwords; i++) { for (u32 i = 0; i < num_dwords; i++) {
comps[i] = ir.GetVectorReg<IR::F32>(src_reg + i); comps[i] = ir.GetVectorReg<IR::F32>(src_reg + i);
} }
@ -426,7 +426,7 @@ void Translator::IMAGE_LOAD(bool has_mip, const GcnInst& inst) {
if (((mimg.dmask >> i) & 1) == 0) { if (((mimg.dmask >> i) & 1) == 0) {
continue; continue;
} }
IR::U32 value = IR::U32{ir.CompositeExtract(texel, i)}; IR::F32 value = IR::F32{ir.CompositeExtract(texel, i)};
ir.SetVectorReg(dest_reg++, value); ir.SetVectorReg(dest_reg++, value);
} }
} }

6
src/shader_recompiler/ir/opcodes.inc
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@ -97,7 +97,7 @@ OPCODE(StoreBufferU32, Void, Opaq
OPCODE(StoreBufferU32x2, Void, Opaque, Opaque, U32x2, ) OPCODE(StoreBufferU32x2, Void, Opaque, Opaque, U32x2, )
OPCODE(StoreBufferU32x3, Void, Opaque, Opaque, U32x3, ) OPCODE(StoreBufferU32x3, Void, Opaque, Opaque, U32x3, )
OPCODE(StoreBufferU32x4, Void, Opaque, Opaque, U32x4, ) OPCODE(StoreBufferU32x4, Void, Opaque, Opaque, U32x4, )
OPCODE(StoreBufferFormatF32, Void, Opaque, Opaque, U32x4, ) OPCODE(StoreBufferFormatF32, Void, Opaque, Opaque, F32x4, )
// Buffer atomic operations // Buffer atomic operations
OPCODE(BufferAtomicIAdd32, U32, Opaque, Opaque, U32 ) OPCODE(BufferAtomicIAdd32, U32, Opaque, Opaque, U32 )
@ -353,8 +353,8 @@ OPCODE(ImageGatherDref, F32x4, Opaq
OPCODE(ImageQueryDimensions, U32x4, Opaque, U32, U1, ) OPCODE(ImageQueryDimensions, U32x4, Opaque, U32, U1, )
OPCODE(ImageQueryLod, F32x4, Opaque, Opaque, ) OPCODE(ImageQueryLod, F32x4, Opaque, Opaque, )
OPCODE(ImageGradient, F32x4, Opaque, Opaque, Opaque, Opaque, Opaque, F32, ) OPCODE(ImageGradient, F32x4, Opaque, Opaque, Opaque, Opaque, Opaque, F32, )
OPCODE(ImageRead, U32x4, Opaque, Opaque, U32, U32, ) OPCODE(ImageRead, F32x4, Opaque, Opaque, U32, U32, )
OPCODE(ImageWrite, Void, Opaque, Opaque, U32, U32, U32x4, ) OPCODE(ImageWrite, Void, Opaque, Opaque, U32, U32, F32x4, )
// Image atomic operations // Image atomic operations
OPCODE(ImageAtomicIAdd32, U32, Opaque, Opaque, U32, ) OPCODE(ImageAtomicIAdd32, U32, Opaque, Opaque, U32, )

4
src/shader_recompiler/ir/reinterpret.h
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@ -12,8 +12,8 @@ namespace Shader::IR {
inline Value ApplySwizzle(IREmitter& ir, const Value& vector, const AmdGpu::CompMapping& swizzle) { inline Value ApplySwizzle(IREmitter& ir, const Value& vector, const AmdGpu::CompMapping& swizzle) {
// Constants are indexed as 0 and 1, and components are 4-7. Thus we can apply a swizzle // Constants are indexed as 0 and 1, and components are 4-7. Thus we can apply a swizzle
// using two vectors and a shuffle, using one vector of constants and one of the components. // using two vectors and a shuffle, using one vector of constants and one of the components.
const auto zero = vector.Type() == Type::U32x4 ? Value{ir.Imm32(0u)} : Value{ir.Imm32(0.f)}; const auto zero = ir.Imm32(0.f);
const auto one = vector.Type() == Type::U32x4 ? Value{ir.Imm32(1u)} : Value{ir.Imm32(1.f)}; const auto one = ir.Imm32(1.f);
const auto constants_vec = ir.CompositeConstruct(zero, one, zero, zero); const auto constants_vec = ir.CompositeConstruct(zero, one, zero, zero);
const auto swizzled = const auto swizzled =
ir.CompositeShuffle(constants_vec, vector, size_t(swizzle.r), size_t(swizzle.g), ir.CompositeShuffle(constants_vec, vector, size_t(swizzle.r), size_t(swizzle.g),