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Replaced V_CMP_EQ_U64 code to match V_CMP_U32 to test

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nickci2002 2025-06-25 11:43:56 -04:00
parent 14d619e5ae
commit 544ff1dfc5
2 changed files with 16 additions and 33 deletions
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2
src/shader_recompiler/frontend/translate/translate.h
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@ -231,7 +231,7 @@ public:
void V_CMP_F32(ConditionOp op, bool set_exec, const GcnInst& inst); void V_CMP_F32(ConditionOp op, bool set_exec, const GcnInst& inst);
void V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst); void V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst);
void V_CMP_U64(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst); void V_CMP_U64(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst);
void V_CMP_EQ_U64(NegateMode negate, const GcnInst& inst); void V_CMP_EQ_U64(ConditionOp op, const GcnInst& inst);
void V_CMP_CLASS_F32(const GcnInst& inst); void V_CMP_CLASS_F32(const GcnInst& inst);
// VOP3a // VOP3a

47
src/shader_recompiler/frontend/translate/vector_alu.cpp
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@ -328,9 +328,9 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
// V_CMP_{OP8}_U64 // V_CMP_{OP8}_U64
case Opcode::V_CMP_EQ_U64: case Opcode::V_CMP_EQ_U64:
return V_CMP_EQ_U64(NegateMode::None, inst); return V_CMP_EQ_U64(ConditionOp::EQ, inst);
case Opcode::V_CMP_NE_U64: case Opcode::V_CMP_NE_U64:
return V_CMP_EQ_U64(NegateMode::Result, inst); return V_CMP_EQ_U64(ConditionOp::LG, inst);
case Opcode::V_CMP_CLASS_F32: case Opcode::V_CMP_CLASS_F32:
return V_CMP_CLASS_F32(inst); return V_CMP_CLASS_F32(inst);
@ -1037,42 +1037,25 @@ void Translator::V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const
// } // }
// } // }
void Translator::V_CMP_EQ_U64(NegateMode negate, const GcnInst& inst) { void Translator::V_CMP_EQ_U64(ConditionOp op, const GcnInst& inst) {
const auto get_src = [&](const InstOperand& operand) { const IR::U64 src0{GetSrc64(inst.src[0])};
switch (operand.field) { const IR::U64 src1{GetSrc64(inst.src[1])};
case OperandField::VccLo: const IR::U1 result = [&] {
return ir.GetVcc(); switch (op) {
case OperandField::ExecLo: case ConditionOp::EQ:
return ir.GetExec(); return ir.IEqual(src0, src1);
case OperandField::ScalarGPR: case ConditionOp::LG: // NE
return ir.GetThreadBitScalarReg(IR::ScalarReg(operand.code)); return ir.INotEqual(src0, src1);
case OperandField::ConstZero:
return ir.Imm1(false);
default: default:
UNREACHABLE(); UNREACHABLE_MSG("Unsupported V_CMP_EQ_U64 condition operation: {}", u32(op));
} }
}; }();
const IR::U1 src0{get_src(inst.src[0])};
auto op = [&inst, this](auto x) {
switch (inst.src[1].field) {
case OperandField::ConstZero:
return ir.LogicalNot(x);
case OperandField::SignedConstIntNeg:
return x;
default:
UNREACHABLE_MSG("unhandled V_CMP_NE_U64 source argument {}", u32(inst.src[1].field));
}
};
auto result = negate == NegateMode::Result ? ir.LogicalNot(op(src0)) : src0;
switch (inst.dst[1].field) { switch (inst.dst[1].field) {
case OperandField::VccLo: case OperandField::VccLo:
ir.SetVcc(result); return ir.SetVcc(result);
break;
case OperandField::ScalarGPR: case OperandField::ScalarGPR:
ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[1].code), result); return ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[1].code), result);
break;
default: default:
UNREACHABLE(); UNREACHABLE();
} }