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shader_recompiler: V_INTERP_MOV_F32
* Should work the same as spirv will emit flat decoration on demand
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4426d7630c
commit
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@ -183,6 +183,7 @@ void DefineEntryPoint(const IR::Program& program, EmitContext& ctx, Id main) {
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ctx.AddCapability(spv::Capability::Float16);
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ctx.AddCapability(spv::Capability::Float16);
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ctx.AddCapability(spv::Capability::Int16);
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ctx.AddCapability(spv::Capability::Int16);
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}
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}
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ctx.AddCapability(spv::Capability::Int64);
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if (info.has_storage_images) {
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if (info.has_storage_images) {
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ctx.AddCapability(spv::Capability::StorageImageExtendedFormats);
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ctx.AddCapability(spv::Capability::StorageImageExtendedFormats);
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}
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}
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@ -86,6 +86,7 @@ void EmitContext::DefineArithmeticTypes() {
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F32[1] = Name(TypeFloat(32), "f32_id");
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F32[1] = Name(TypeFloat(32), "f32_id");
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S32[1] = Name(TypeSInt(32), "i32_id");
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S32[1] = Name(TypeSInt(32), "i32_id");
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U32[1] = Name(TypeUInt(32), "u32_id");
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U32[1] = Name(TypeUInt(32), "u32_id");
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U64 = Name(TypeUInt(64), "u64_id");
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for (u32 i = 2; i <= 4; i++) {
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for (u32 i = 2; i <= 4; i++) {
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if (info.uses_fp16) {
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if (info.uses_fp16) {
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@ -179,6 +179,7 @@ public:
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// Vector interpolation
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// Vector interpolation
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void V_INTERP_P2_F32(const GcnInst& inst);
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void V_INTERP_P2_F32(const GcnInst& inst);
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void V_INTERP_MOV_F32(const GcnInst& inst);
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// Data share
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// Data share
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void DS_SWIZZLE_B32(const GcnInst& inst);
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void DS_SWIZZLE_B32(const GcnInst& inst);
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@ -620,12 +620,12 @@ void Translator::V_SUBREV_I32(const GcnInst& inst) {
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}
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}
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void Translator::V_MAD_U64_U32(const GcnInst& inst) {
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void Translator::V_MAD_U64_U32(const GcnInst& inst) {
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const auto src0 = GetSrc<IR::U32>(inst.src[0]);
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const auto src0 = GetSrc<IR::U32>(inst.src[0]);
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const auto src1 = GetSrc<IR::U32>(inst.src[1]);
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const auto src1 = GetSrc<IR::U32>(inst.src[1]);
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const auto src2 = GetSrc64<IR::U64>(inst.src[2]);
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const auto src2 = GetSrc64<IR::U64>(inst.src[2]);
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const IR::U64 mul_result = ir.UConvert(64, ir.IMul(src0, src1));
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//const IR::U64 mul_result = ir.UConvert(64, ir.IMul(src0, src1));
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const IR::U64 mul_result = ir.PackUint2x32(ir.CompositeConstruct(ir.IMul(src0, src1), ir.Imm32(0U)));
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const IR::U64 sum_result = ir.IAdd(mul_result, src2);
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const IR::U64 sum_result = ir.IAdd(mul_result, src2);
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SetDst64(inst.dst[0], sum_result);
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SetDst64(inst.dst[0], sum_result);
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@ -12,14 +12,23 @@ void Translator::V_INTERP_P2_F32(const GcnInst& inst) {
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ir.SetVectorReg(dst_reg, ir.GetAttribute(attrib, inst.control.vintrp.chan));
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ir.SetVectorReg(dst_reg, ir.GetAttribute(attrib, inst.control.vintrp.chan));
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}
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}
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void Translator::V_INTERP_MOV_F32(const GcnInst& inst) {
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const IR::VectorReg dst_reg{inst.dst[0].code};
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auto& attr = info.ps_inputs.at(inst.control.vintrp.attr);
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const IR::Attribute attrib{IR::Attribute::Param0 + attr.param_index};
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ir.SetVectorReg(dst_reg, ir.GetAttribute(attrib, inst.control.vintrp.chan));
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}
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void Translator::EmitVectorInterpolation(const GcnInst& inst) {
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void Translator::EmitVectorInterpolation(const GcnInst& inst) {
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switch (inst.opcode) {
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switch (inst.opcode) {
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case Opcode::V_INTERP_P1_F32:
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case Opcode::V_INTERP_P1_F32:
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return;
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return;
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case Opcode::V_INTERP_P2_F32:
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case Opcode::V_INTERP_P2_F32:
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return V_INTERP_P2_F32(inst);
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return V_INTERP_P2_F32(inst);
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case Opcode::V_INTERP_MOV_F32:
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return V_INTERP_MOV_F32(inst);
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default:
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default:
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info.translation_failed = true;
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LogMissingOpcode(inst);
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}
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}
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}
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}
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