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fix V_ADDC_U32 carry

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Vinicius Rangel 2024-07-23 15:52:01 -03:00
parent 510072b4f4
commit c73aff3f8d
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GPG Key ID: A5B154D904B761D9
2 changed files with 6 additions and 4 deletions
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9
src/shader_recompiler/frontend/translate/vector_alu.cpp
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@ -97,14 +97,15 @@ void Translator::V_ADDC_U32(const GcnInst& inst) {
const auto src0 = GetSrc<IR::U32>(inst.src[0]); const auto src0 = GetSrc<IR::U32>(inst.src[0]);
const auto src1 = GetSrc<IR::U32>(inst.src[1]); const auto src1 = GetSrc<IR::U32>(inst.src[1]);
IR::U32 scarry; IR::U1 scarry;
if (inst.src_count == 3) { // VOP3 if (inst.src_count == 3) { // VOP3
scarry = GetSrc<IR::U32>(inst.src[2]); scarry = ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[2].code));
} else { // VOP2 } else { // VOP2
scarry = ir.GetVccLo(); scarry = ir.GetVcc();
} }
IR::U32 result = ir.IAdd(ir.IAdd(src0, src1), scarry); const IR::U32 carry_v{ir.Select(scarry, ir.Imm32(1), ir.Imm32(0))};
IR::U32 result = ir.IAdd(ir.IAdd(src0, src1), carry_v);
const IR::VectorReg dst_reg{inst.dst[0].code}; const IR::VectorReg dst_reg{inst.dst[0].code};
ir.SetVectorReg(dst_reg, result); ir.SetVectorReg(dst_reg, result);

1
src/shader_recompiler/ir/ir_emitter.cpp
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@ -243,6 +243,7 @@ U1 IREmitter::GetExec() {
} }
U1 IREmitter::GetVcc() { U1 IREmitter::GetVcc() {
// FIXME Should it be a thread bit?
return Inst<U1>(Opcode::GetVcc); return Inst<U1>(Opcode::GetVcc);
} }