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vector_alu: Fix V_CMP_U64 (#3823)

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* vector_alu: Fix V_CMP_U64

* vector_alu: Also handle vcc in V_CMP_U64
This commit is contained in:
TheTurtle
2025-11-24 03:26:34 +02:00
committed by GitHub
parent f6ae5544fd
commit f1a8b7d85e
1 changed files with 14 additions and 9 deletions
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21
src/shader_recompiler/frontend/translate/vector_alu.cpp
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@@ -1043,20 +1043,25 @@ void Translator::V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const
} }
void Translator::V_CMP_U64(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst) { void Translator::V_CMP_U64(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst) {
const IR::U64 src0{GetSrc64(inst.src[0])}; ASSERT(inst.src[1].field == OperandField::ConstZero);
const IR::U64 src1{GetSrc64(inst.src[1])}; const IR::U1 src0 = [&] {
switch (inst.src[0].field) {
case OperandField::ScalarGPR:
return ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[0].code));
case OperandField::VccLo:
return ir.GetVcc();
default:
UNREACHABLE_MSG("src0 = {}", u32(inst.src[0].field));
}
}();
const IR::U1 result = [&] { const IR::U1 result = [&] {
switch (op) { switch (op) {
case ConditionOp::EQ: case ConditionOp::EQ:
return ir.IEqual(src0, src1); return ir.LogicalNot(src0);
case ConditionOp::LG: // NE case ConditionOp::LG: // NE
return ir.INotEqual(src0, src1); return src0;
case ConditionOp::GT: case ConditionOp::GT:
if (src1.IsImmediate() && src1.U64() == 0) {
ASSERT(inst.src[0].field == OperandField::ScalarGPR);
return ir.GroupAny(ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[0].code))); return ir.GroupAny(ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[0].code)));
}
return ir.IGreaterThan(src0, src1, is_signed);
default: default:
UNREACHABLE_MSG("Unsupported V_CMP_U64 condition operation: {}", u32(op)); UNREACHABLE_MSG("Unsupported V_CMP_U64 condition operation: {}", u32(op));
} }