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https://github.com/shadps4-emu/shadPS4.git
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41d64a200d
* shader_recompiler: Add swizzle support for unsupported formats. * renderer_vulkan: Rework MRT swizzles and add unsupported format swizzle support. * shader_recompiler: Clean up swizzle handling and handle ImageRead storage swizzle. * shader_recompiler: Fix type errors * liverpool_to_vk: Remove redundant clear color swizzles. * shader_recompiler: Reduce CompositeConstruct to constants where possible. * shader_recompiler: Fix ImageRead/Write and StoreBufferFormatF32 types. * amdgpu: Add a few more unsupported format remaps.
216 lines
8.3 KiB
C++
216 lines
8.3 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/backend/spirv/emit_spirv_instructions.h"
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#include "shader_recompiler/backend/spirv/spirv_emit_context.h"
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namespace Shader::Backend::SPIRV {
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template <typename... Args>
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Id EmitCompositeConstruct(EmitContext& ctx, IR::Inst* inst, Args&&... args) {
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return inst->AreAllArgsImmediates() ? ctx.ConstantComposite(args...)
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: ctx.OpCompositeConstruct(args...);
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}
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Id EmitCompositeConstructU32x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2) {
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return EmitCompositeConstruct(ctx, inst, ctx.U32[2], e1, e2);
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}
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Id EmitCompositeConstructU32x3(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3) {
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return EmitCompositeConstruct(ctx, inst, ctx.U32[3], e1, e2, e3);
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}
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Id EmitCompositeConstructU32x4(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3, Id e4) {
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return EmitCompositeConstruct(ctx, inst, ctx.U32[4], e1, e2, e3, e4);
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}
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Id EmitCompositeExtractU32x2(EmitContext& ctx, Id composite, u32 index) {
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return ctx.OpCompositeExtract(ctx.U32[1], composite, index);
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}
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Id EmitCompositeExtractU32x3(EmitContext& ctx, Id composite, u32 index) {
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return ctx.OpCompositeExtract(ctx.U32[1], composite, index);
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}
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Id EmitCompositeExtractU32x4(EmitContext& ctx, Id composite, u32 index) {
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return ctx.OpCompositeExtract(ctx.U32[1], composite, index);
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}
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Id EmitCompositeInsertU32x2(EmitContext& ctx, Id composite, Id object, u32 index) {
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return ctx.OpCompositeInsert(ctx.U32[2], object, composite, index);
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}
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Id EmitCompositeInsertU32x3(EmitContext& ctx, Id composite, Id object, u32 index) {
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return ctx.OpCompositeInsert(ctx.U32[3], object, composite, index);
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}
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Id EmitCompositeInsertU32x4(EmitContext& ctx, Id composite, Id object, u32 index) {
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return ctx.OpCompositeInsert(ctx.U32[4], object, composite, index);
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}
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Id EmitCompositeShuffleU32x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1) {
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return ctx.OpVectorShuffle(ctx.U32[2], composite1, composite2, comp0, comp1);
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}
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Id EmitCompositeShuffleU32x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
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u32 comp2) {
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return ctx.OpVectorShuffle(ctx.U32[3], composite1, composite2, comp0, comp1, comp2);
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}
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Id EmitCompositeShuffleU32x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
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u32 comp2, u32 comp3) {
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return ctx.OpVectorShuffle(ctx.U32[4], composite1, composite2, comp0, comp1, comp2, comp3);
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}
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Id EmitCompositeConstructF16x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2) {
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return EmitCompositeConstruct(ctx, inst, ctx.F16[2], e1, e2);
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}
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Id EmitCompositeConstructF16x3(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3) {
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return EmitCompositeConstruct(ctx, inst, ctx.F16[3], e1, e2, e3);
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}
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Id EmitCompositeConstructF16x4(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3, Id e4) {
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return EmitCompositeConstruct(ctx, inst, ctx.F16[4], e1, e2, e3, e4);
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}
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Id EmitCompositeExtractF16x2(EmitContext& ctx, Id composite, u32 index) {
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return ctx.OpCompositeExtract(ctx.F16[1], composite, index);
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}
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Id EmitCompositeExtractF16x3(EmitContext& ctx, Id composite, u32 index) {
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return ctx.OpCompositeExtract(ctx.F16[1], composite, index);
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}
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Id EmitCompositeExtractF16x4(EmitContext& ctx, Id composite, u32 index) {
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return ctx.OpCompositeExtract(ctx.F16[1], composite, index);
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}
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Id EmitCompositeInsertF16x2(EmitContext& ctx, Id composite, Id object, u32 index) {
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return ctx.OpCompositeInsert(ctx.F16[2], object, composite, index);
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}
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Id EmitCompositeInsertF16x3(EmitContext& ctx, Id composite, Id object, u32 index) {
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return ctx.OpCompositeInsert(ctx.F16[3], object, composite, index);
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}
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Id EmitCompositeInsertF16x4(EmitContext& ctx, Id composite, Id object, u32 index) {
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return ctx.OpCompositeInsert(ctx.F16[4], object, composite, index);
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}
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Id EmitCompositeShuffleF16x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1) {
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return ctx.OpVectorShuffle(ctx.F16[2], composite1, composite2, comp0, comp1);
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}
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Id EmitCompositeShuffleF16x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
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u32 comp2) {
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return ctx.OpVectorShuffle(ctx.F16[3], composite1, composite2, comp0, comp1, comp2);
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}
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Id EmitCompositeShuffleF16x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
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u32 comp2, u32 comp3) {
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return ctx.OpVectorShuffle(ctx.F16[4], composite1, composite2, comp0, comp1, comp2, comp3);
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}
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Id EmitCompositeConstructF32x2(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2) {
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return EmitCompositeConstruct(ctx, inst, ctx.F32[2], e1, e2);
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}
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Id EmitCompositeConstructF32x3(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3) {
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return EmitCompositeConstruct(ctx, inst, ctx.F32[3], e1, e2, e3);
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}
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Id EmitCompositeConstructF32x4(EmitContext& ctx, IR::Inst* inst, Id e1, Id e2, Id e3, Id e4) {
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return EmitCompositeConstruct(ctx, inst, ctx.F32[4], e1, e2, e3, e4);
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}
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Id EmitCompositeExtractF32x2(EmitContext& ctx, Id composite, u32 index) {
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return ctx.OpCompositeExtract(ctx.F32[1], composite, index);
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}
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Id EmitCompositeExtractF32x3(EmitContext& ctx, Id composite, u32 index) {
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return ctx.OpCompositeExtract(ctx.F32[1], composite, index);
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}
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Id EmitCompositeExtractF32x4(EmitContext& ctx, Id composite, u32 index) {
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return ctx.OpCompositeExtract(ctx.F32[1], composite, index);
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}
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Id EmitCompositeInsertF32x2(EmitContext& ctx, Id composite, Id object, u32 index) {
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return ctx.OpCompositeInsert(ctx.F32[2], object, composite, index);
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}
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Id EmitCompositeInsertF32x3(EmitContext& ctx, Id composite, Id object, u32 index) {
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return ctx.OpCompositeInsert(ctx.F32[3], object, composite, index);
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}
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Id EmitCompositeInsertF32x4(EmitContext& ctx, Id composite, Id object, u32 index) {
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return ctx.OpCompositeInsert(ctx.F32[4], object, composite, index);
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}
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Id EmitCompositeShuffleF32x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1) {
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return ctx.OpVectorShuffle(ctx.F32[2], composite1, composite2, comp0, comp1);
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}
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Id EmitCompositeShuffleF32x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
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u32 comp2) {
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return ctx.OpVectorShuffle(ctx.F32[3], composite1, composite2, comp0, comp1, comp2);
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}
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Id EmitCompositeShuffleF32x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
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u32 comp2, u32 comp3) {
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return ctx.OpVectorShuffle(ctx.F32[4], composite1, composite2, comp0, comp1, comp2, comp3);
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}
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void EmitCompositeConstructF64x2(EmitContext&) {
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UNREACHABLE_MSG("SPIR-V Instruction");
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}
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void EmitCompositeConstructF64x3(EmitContext&) {
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UNREACHABLE_MSG("SPIR-V Instruction");
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}
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void EmitCompositeConstructF64x4(EmitContext&) {
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UNREACHABLE_MSG("SPIR-V Instruction");
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}
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void EmitCompositeExtractF64x2(EmitContext&) {
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UNREACHABLE_MSG("SPIR-V Instruction");
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}
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void EmitCompositeExtractF64x3(EmitContext&) {
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UNREACHABLE_MSG("SPIR-V Instruction");
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}
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void EmitCompositeExtractF64x4(EmitContext&) {
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UNREACHABLE_MSG("SPIR-V Instruction");
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}
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Id EmitCompositeInsertF64x2(EmitContext& ctx, Id composite, Id object, u32 index) {
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return ctx.OpCompositeInsert(ctx.F64[2], object, composite, index);
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}
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Id EmitCompositeInsertF64x3(EmitContext& ctx, Id composite, Id object, u32 index) {
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return ctx.OpCompositeInsert(ctx.F64[3], object, composite, index);
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}
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Id EmitCompositeInsertF64x4(EmitContext& ctx, Id composite, Id object, u32 index) {
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return ctx.OpCompositeInsert(ctx.F64[4], object, composite, index);
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}
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Id EmitCompositeShuffleF64x2(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1) {
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return ctx.OpVectorShuffle(ctx.F64[2], composite1, composite2, comp0, comp1);
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}
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Id EmitCompositeShuffleF64x3(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
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u32 comp2) {
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return ctx.OpVectorShuffle(ctx.F64[3], composite1, composite2, comp0, comp1, comp2);
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}
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Id EmitCompositeShuffleF64x4(EmitContext& ctx, Id composite1, Id composite2, u32 comp0, u32 comp1,
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u32 comp2, u32 comp3) {
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return ctx.OpVectorShuffle(ctx.F64[4], composite1, composite2, comp0, comp1, comp2, comp3);
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}
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} // namespace Shader::Backend::SPIRV
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